In integrated circuit art, a commonly used method for forming interconnect structures, which include metal lines and vias, is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper is commonly used in damascene structures because of its low resistivity. Typically, an interconnect structure is formed of a plurality of metallization layers, each including a plurality of copper lines. Copper lines in different metallization layers are interconnected by vias. During the formation of one metallization layer, the underlying metallization layer will typically have portions exposed to open air.
FIG. 1 illustrates a cross-sectional view of an intermediate stage in the formation of a conventional damascene structure. Copper line 2 is formed in dielectric layer 4. Dielectric layer 6 is formed over copper line 2 and dielectric layer 4. Opening 8 is then formed (using a patterned photo resist (not shown)) in dielectric layer 6 to expose the underlying copper line 2. The formation of opening 8 is performed in open air. Affected by oxygen and moisture in the air, an exposed portion of copper line 2 is oxidized, forming copper oxide layer 10. After the formation of opening 8, the photo resist is removed by ashing. The photo resist ashing process may further increase the thickness of copper oxide layer 10. Copper oxide layer 10 adversely affects the electrical conduction between metal line 2 and the subsequently formed metal feature in opening 8, and thus has to be removed.
Conventionally, a furnace baking is performed to remove copper oxide layer 10. The furnace baking is performed at a pressure of one atmosphere, with hydrogen introduced into the furnace. With an elevated temperature, copper oxide layer 10 is reduced to copper, while the oxygen in copper oxide layer 10 reacts with hydrogen to form water (H2O). Typically, the furnace baking may last two hours or even longer.
The wafer containing the structure shown in FIG. 1 is then transferred to a vacuum environment to form a barrier layer and a copper seed layer. However, during the transferring, the wafer is exposed to open air, and hence a thin copper oxide layer is formed again on the exposed portion of copper line 2. Also, moisture may be trapped in the wafer. The Q-time, which is the time the wafer is exposed to open air, needs to be tightly controlled to reduce the thickness of the copper oxide layer. The controlling of the Q-time, however, can only make the copper oxide thinner, but cannot eliminate its formation. Therefore, in the vacuum environment, an additional removal process is performed to remove the thin copper oxide layer. The removal of the thin copper oxide layer may include a degas process (at an elevated temperature with no hydrogen introduced) to remove moisture, and a plasma clean at room temperature (with hydrogen as a process gas) to remove the thin copper oxide layer.
With a long furnace baking time and the additional copper oxide removal process in the vacuum environment, the throughput of the manufacturing process is adversely affected. The seemingly redundant, however necessary, copper removal processes also result in the increase in the manufacturing cost. New methods are thus needed to increase the throughput and to reduce the manufacturing cost.